1. Field of the Invention
The invention relates to a structure of a sweep-type fingerprint sensing chip capable of resisting electrostatic discharge, and a method of fabricating the same. The invention correlates to the commonly assigned patents of: (a). U.S. patent application Ser. No. 10/403,052 (US20030190061A1), filed on Apr. 1, 2003, entitled “CAPACITIVE FINGERPRINT SENSOR,” and published on Oct. 9, 2003 as US20030190061A1; (b). U.S. patent application Ser. No. 10/434,833 (US20030215976A1), filed on May 13, 2003, entitled “PRESSURE TYPE FINGERPRINT SENSOR FABRICATION METHOD”; (c). U.S. patent application Ser. No. 10/414,214 (US20040208345A1), filed on Apr. 16, 2003, and entitled “THERMOELECTRIC SENSOR FOR FINGERPRINT THERMAL IMAGING”; (d). U.S. patent application Ser. No. 10/638,371 (US20040046574A1), filed on Aug. 12, 2003, and entitled “CAPACITIVE MICRO PRESSURE SENSING MEMBER AND FINGERPRINT SENSOR USING THE SAME”; (e). U.S. patent application Ser. No. 10/429,733, filed on May 6, 2003, and entitled “CAPACITIVE FINGERPRINT SENSOR AGAINST ESD DAMAGE AND CONTAMINATION INTERFERENCE AND A METHOD FOR MANUFACTURING THE SAME”; (f). U.S. patent application Ser. No. 10/825,313 (US20050231213A1), filed on Apr. 16, 2004 and entitled “CHIP-TYPE SENSOR AGAINST ESD AND STRESS DAMAGES AND CONTAMINATION INTERFERENCE”; and (g) U.S. patent application Ser. No. 11/376,179 filed on Mar. 16, 2006, and entitled “LINEAR IMAGE SENSING DEVICE WITH IMAGE MATCHING FUNCTION AND PROCESSING METHOD THEREFOR”.
2. Description of the Related Art
Traditionally, IC design focuses on the electrical characteristics of the IC chip and the chip is packaged inside a protection body to prevent it from damaging by the external force or ESD (Electrostatic Discharge).
Nevertheless, some new applications need the chip surface to be partially exposed to the environment, for example, a chip-type fingerprint sensor, as disclosed in the above-mentioned application entitled “CAPACITIVE FINGERPRINT SENSOR”, needs to provide a chip surface to be in contact with the finger, so that the ridges of the finger may be read for identification or verification.
Consequently, the mechanical property of the chip surface has to be well considered so that the protection structure of the chip can withstand the finger's vertical force and the ESD damage from the finger or other approaching objects.
In the basic structure of the conventional capacitive fingerprint sensor chip, associated sense and control/processing circuits are formed in a silicon substrate, a plurality of metal plates arranged in an array is disposed on the chip and serves as the sense electrodes (the portion below the sense electrodes and including the sense and control/processing circuits and the silicon substrate is referred to as a substrate structure), and a dielectric layer is formed on an external surface of the chip to serve as the dielectric medium of the sense capacitor between the finger and each sense electrode as well as the passivation layer for the exposed chip surface. In order to achieve the force-withstanding and wear-resistant properties of the chip surface, the prior art utilizes a hard coating material to form the passivation layer on the external surface. For example, all of the WO 01/06448A1, WO 03/098541A1, U.S. Pat. No. 6,091,082, EP1256899, U.S. Pat. Nos. 6,114,862, and 6,515,488 patents disclose this architecture. In brief, the prior art patents include a hard layer, such as the silicon nitride, silicon carbide, aluminum oxide or diamond, formed above the substrate structure, or include a soft dielectric material, such as the silicon dioxide, formed between the hard layer and the substrate structure.
The hard layer, such as the silicon nitride, silicon carbide, aluminum oxide or diamond, has the good mechanical strength. However, when the hard layer is formed on the substrate structure using the semiconductor processing method, the thickness limitation thereof will be encountered because of the residual thermal stress between the hard layer and the substrate structure. In general, the silicon nitride, silicon carbide, aluminum oxide or diamond exhibits the tensile stress against the substrate structure mainly including the silicon substrate. If the hard layer is thick, it tends to crack owing to the stress. Consequently, the chip tends to crack and cannot withstand the ESD damage or force impingement. Typically, a single hard layer or a bimorph layer around 2 microns or less is formed on the sensor surface to overcome the above-mentioned problems due to the process limitation available in semiconductor factory. Nevertheless, a relatively large residual thermal stress still exists therein, which will induce material defects therein and form stress concentration points around those defects, and may easily be broken by external force or ESD. Hence, it is an important subject to reduce the residual thermal stress and thus increase the thickness of the protection structure because the mechanical strength is directly proportional to the third power of the thickness.
In addition to the above-mentioned mechanical property such as the force-withstanding property of the chip surface, the ESD damage is another important subject. There are two ways for solving the ESD damage. One way is to increase the thickness of the passivation layer because the electrostatic field intensity that may be withstood is directly proportional to the square of the thickness.
In the typical commercial IC (integrated circuit) process, for example, the thickness of the passivation layer (usually including a bimorph structure composed of the silicon dioxide and the silicon nitride) is about 1 micron, and the ESD damage voltage (air mode) that may be withstood is about 1 KV. Also, because the structure of the passivation layer of the above-mentioned patents cannot be effectively increased in thickness, the protection against the ESD damage cannot be achieved only depending on the material property of the passivation layer.
Hence, the other way is to utilize the exposed metal mesh structure to conduct the electrostatic charges to the ground, as mentioned in the above-mentioned patents WO 01/06448A1, WO 03/098541A1 and EP1256899. The concept of using the conductor to conduct the electrostatic charges has been adopted in many electronics products. However, the key issues having to be considered is the process and material compatibility when implementing the exposed metal mesh on the fingerprint sensor chip to solve the ESD problem.
For example, WO 01/06448A1 patent discloses this idea of an exposed metal mesh structure serving as the conducting structure for the electrostatic charges. However, the used manufacturing processes, the single layer TiN serving as the metal sense electrode material, and the exposed metal mesh material is not a standard processing step in commercial IC foundry. In addition, the thin TiN film may have the step coverage problem when it is formed on the rugged chip surface. Furthermore, because of the high resistivity of the TiN film, an arbitrarily large current caused by the electrostatic charges flowing therethrough may burn it out due to the joule heating effect. In addition, WO 03/098541A1 patent also discloses an exposed metal mesh structure, which is substantially the same as that of the WO 01/06448A1 patent, as the conducting structure for the electrostatic charges. The main difference therebetween is that the external surface of the exposed metal includes the gold material, which may solve the erosion problem of the metal. However, the manufacturing processes cannot be compatible with the silicon IC manufacturing processes because the gold material may cause contamination.
EP1256899 patent discloses a tungsten metal mesh design. However, in the step of depositing the tungsten metal and the subsequent etching back step, small cavities, which are regarded as defects and cause the problems such as stress concentration points around those defects, are formed on the sensor surface of the passivation layer of silicon carbide. When the fingernail unintentionally hits the external surface of the sensor, the sensor may be damaged. Furthermore, the small cavities make the surface of the passivation layer hydrophilic. Thus, the moisture of the finger tends to diffuse after the finger contacts the external surface, and the image quality is deteriorated accordingly. Consequently, a method is needed for refilling the small cavities with the silicon dioxide so as to make the external surface smooth by depositing the silicon dioxide followed by the CMP process. However, this way makes the manufacturing processes too complicated and is not suitable for the general manufacturing procedures of the commercial IC foundry.
To solve the above-mentioned problems, the above-mentioned (e) patent has disclosed a capacitive fingerprint sensor against ESD damage and contamination interference, wherein the sensor includes a silicon substrate formed with integrated circuits, a plurality of plate electrodes, a metal mesh, a plurality of ESD units, a plurality of bonding pads and a passivation layer. The metal mesh crisscrosses between the plate electrodes, is flush with the plate electrodes, and encloses each of the plate electrodes. The metal mesh is grounded. The ESD units are connected to the metal mesh and are formed between a predetermined number of adjacent plate electrodes among the plate electrodes, wherein the number of ESD units is smaller than the number of plate electrodes.
Heretofore, the above-mentioned prior arts consider the effect against the ESD damage in the area-type fingerprint sensing chip. Taking the product LTT-C500 manufactured by LIGHTUNING TECH. INC., the sensing area of the product is equal to 192 pixels×236 pixels (9.6 mm×11.8 mm), and the chip size is about 10 mm×12 mm. It is clear that the main chip area is formed with the two-dimensional sensing member array, so the design against the ESD damage is made according to the consideration of the sensing area. FIG. 1 is a schematic illustration showing the exterior of an area-type fingerprint sensing chip. Referring to FIG. 1, the area-type fingerprint sensing chip 100 includes a two-dimensional sensing member array 102 formed on a semiconductor substrate 101 and an associated read and control circuit 103, such as a gain adjustable amplifier, an analog-to-digital converter and a control logic, located around the two-dimensional sensing member array 102.
FIG. 2 is a schematically cross-sectional view taken along the line A-A of FIG. 1 after the fingerprint sensing chip of FIG. 1 is packaged. As shown in FIG. 2, the area-type fingerprint sensing chip 100 is placed on a package substrate 110 and wired and encapsulated. An encapsulant 120 seals the read and control circuit 103 to protect the circuit 103 from being damaged by a finger F or an external force. As shown in FIG. 2, this area-type fingerprint sensing chip protects its associated circuit, by way of package including encapsulation and transfer molding, from the external environment interference and the ESD damage. Consequently, the considerations of the main environment interference and the ESD damage focus on the two-dimensional sensing member array 102, which is the key point of the above-mentioned prior art.
However, the sensing area of the conventional chip-type fingerprint sensor is larger than 9 mm×9 mm due to the limitation of the dimension of the finger. Furthermore, only 50 to 70 effective chips can be formed on a 6″ wafer due to the limitation of manufacturing the silicon integrated circuit. So, the cost of the fingerprint sensor is very high, which restricts its applications to various consumer electronic products, such as a notebook computer, a mobile phone, a personal digital assistant, a computer peripheral product, and even a personal ID card combined with the fingerprint sensor.
In order to overcome the above-mentioned problem in cost, the length of the conventional two-dimensional chip-type fingerprint sensor may be shortened. In this case, the finger sweeps across the surface of the chip such that multiple fingerprint fragment images are obtained and then reconstructed into a complete image. Thereafter, the finger may sweep across the surface of the chip so that a fingerprint template is obtained. Thus, the user can be identified by comparing the fingerprint template with the reference template. For example, the chip size of the above-mentioned (g) patent is smaller than 1.5 mm in the sliding direction of the finger, and the length of the sensing member is 0.4 mm (8 pixels). The schematic illustration is shown in FIG. 3. FIG. 3 is a schematic illustration showing the exterior of a sweep-type fingerprint sensing chip. FIG. 4 is a schematically cross-sectional view taken along the line B-B of FIG. 3 after the fingerprint sensing chip of FIG. 3 is packaged. As shown in FIGS. 3 and 4, the sweep-type fingerprint sensing chip 200 includes a sensing member array 202 formed on a semiconductor substrate 201 and a read and control circuit 203, including a gain adjustable amplifier, an analog-to-digital converter and a control logic, disposed around the sensing member array 202. If the sweep-type fingerprint sensing chip 200 is placed on a package substrate 210 for package including wiring and encapsulating processes in a manner similar to the conventional area-type fingerprint sensing chip 100, the encapsulant 220 encapsulates the read and control circuit 203 to protect it. As shown in FIGS. 3 and 4, when the finger F sweeps across the surface of the packaged chip, the finger cannot easily touch the sensing area of the chip because the peripheral encapsulating height is too high (usually higher than several hundreds of microns). This is because the protection encapsulants at two sides are too high such that the finger F cannot easily touch the chip surface. Thus, the package thereof has to expose the read and control circuit 203, as shown in FIG. 5, and the chip surface has to be flat such that the finger can contact the chip surface effectively.
FIG. 5 is a schematic illustration showing a package structure of a conventional sweep-type fingerprint sensing chip. As shown in FIG. 5, in order to make the sweeping finger F touch the sensing member array 202 easily, the package has to be made to have the flat plane, or only a small height difference, such as several microns, is allowed. The area occupied by the read and control circuit 203 around the sensing member array 202 is almost one half of the overall sweep-type fingerprint sensing chip 200. Consequently, if the requirement of the flat surface on which the finger sweeps has to be met, the key point of the ESD protection aims at the peripheral circuit, which is different from the area-type sensor with the key protection point on the two-dimensional sensing member array, as mentioned hereinabove.
When the chip encounters the ESD interference, the exposed read and control circuit 203 in FIG. 5 tends to be damaged. In one case, the latch-up effect tends to occur and the chip cannot be used until it is reset. In another case, the chip is totally damaged by the electrostatic charges. FIGS. 6A to 6C are schematic illustrations showing conventional structures of the sweep-type fingerprint sensing chip. As shown in FIGS. 6A to 6C, the conventional solution is to dispose a metal layer 230, which is to be grounded, on the sweep-type fingerprint sensing chip 200 by way of coating or plating. However, this solution tends to cause the tip discharge under the ESD interference due to the uneven chip surface, and the read and control circuit 203 is thus damaged. For example, when the electrostatic charge 250 hits the chip, the tip 204 causes the tip discharge to damage the read and control circuit 203. In addition, a serious parasitic capacitor between the grounded metal layer 230 and the read and control circuit 203 tends to occur because the passivation layer 205 made of, for example, silicon dioxide and silicon nitride covering the external surface of the sweep-type fingerprint sensing chip 200 in the semiconductor foundry does not have a very small dielectric constant and the thickness thereof is only about 1 micron. In addition, the grounding condition of the metal layer 230 tends to interfere with the operation of the read and control circuit 203 due to the floating grounding voltage. Thus, it is problematic to dispose a metal film on the passivation layer of the read and control circuit 203 directly.